Hardware → Maple Bus
"Maple" is Sega's proprietary peripheral interface, and supports the connection of peripheral devices such as control pads and light guns through four ports. The Maple interface sends/receives serial data with the devices. The contents of the data are defined by the Maple Bus protocol. (The controller has no effect on the details of the protocol.) Protocol organization and analysis is handled by the SH4 CPU.
The hardware includes one port consisting of two lines, SDCKA and SDCKB, and data transfers are performed in synchronous serial mode. Data is transferred through half-duplex bi-directional transfer with a maximum data transfer rate of 2Mbps and a minimum data transfer rate of 250Kbps. The minimum data transfer unit is one frame, each of which begins with the START pattern that is indicated at the beginning of the data transfer, followed by a DATA pattern ranging in length from 4 to 1024 bytes, the parity bit, and then the END pattern. The eight parity bits are added automatically by the hardware when the data is sent, and are removed when the data is received.
The following register sets are provided for the Maple interface. (Details on each register are provided in the list of registers.)
A command file is set up in system memory, containing the instructions (settings such as the communications port selection, the received data storage address, and the transfer data length) for the Maple controller and the transmission data. The command file consists of units formed by "instruction to the controller," "received data storage address," and "transmission data," in that order. Each of these units are located consecutively in system memory.
The controller can be started up by two methods: by software, or by hardware in synchronization with the V-BLANK signal. These methods are selected through the trigger selection register (SB_MDTSEL). When startup by the V-BLANK signal is selected, delayed startup can be selected through the system register (SB_MSYS) setting.
When the DMA enable register (SB_MDEN) and the DMA start register (SB_MDST) have been set by the SH4, the controller starts up and loads in the command file. The controller follows the instructions, sending the transmission data in system memory indicated by the DMA command table address register (SB_MDSTAR) in the specified length to the target port, and then waits to receive a response. When data is received, the controller writes that data in system memory, starting from the received data store address that was set in the instructions. After receiving data, the controller continues executing the instructions in sequence until it detects the end of the command file. (Accesses between the controller and system memory are all performed through DMA in ch0-DDT mode, and data is sent and received in units of 32 bytes.)
If, as a result of being disconnected or some other problem, the peripheral device does not respond (times out), then 0xFFFFFFFF is written to the first 32 bits of the received data storage address as "disconnected" processing. 0xFFFFFF00 is written if a parity error occurs during reception of serial data.
Instructions to the Maple interface consist of 32 bits of data as shown above, and are set up in system memory.
An instruction consists of an End Flag bit, which indicates the end of the command file; the Port Select bits, which select the active port that is the target of the transmission/reception operation; the Pattern selection bits; and the Transfer Length bits.
When Maple detects a "1" in the End Flag bit, it terminates processing with this instruction. (The End Flag must be set to "1" in the last instruction in the transmission data.) When the pattern selection bits are set to "000," Maple outputs the data that is to be sent. If any other pattern is selected, the port outputs the information pattern only, and the transmission data length specification becomes invalid. "111" (NOP) is used to extend processing for a certain length of time. when the pattern "010" (Light-Gun mode) is selected, the End Flag bit of that instruction must be set to "1". All subsequent instructions are invalid until the pattern "100" (return from Light-Gun mode) is detected.
End Flag: Command file end bit
Port Select: Port selection bits… These bits select the port that is the target of the transmission/reception operation.
Pattern: Pattern selection bits
Transfer Length: Transfer data length selection bits
Data is received from peripheral devices in 4-byte units, and is first loaded in a 32-byte reception FIFO. As soon as the FIFO becomes full, the data is transferred to the received data storage address in system memory. However, as soon as reception ends, even if the FIFO buffer is not full, an remaining data is regarded as invalid data and is transferred as 32 bytes.
The received data storage address area is from 0x00C00000 to 0x00FFFFE0 in system memory. (Specify "0" for the lower five bits of the address that indicates the 32 bytes that are transferred.)
Register Map
The registers that are used only by the Maple interface are in the area (from 0x005F 6C00 to 0x005F 6CFF) described in the system mapping table in section 2.1.
The mapping of the registers that are used by Maple is shown below. (Refer to section 8.4.1.2 for details on individual registers.)
Table 5-1 Maple Register Map
* In the above table, in the "Reset Initialize" column, "Not Initialized" indicates that the register value is undefined after a system reset. In all other cases, the value shown indicates the value that is set in that register after a system reset.
Operating Sequence
There are two interface operating sequences: the normal sequence, and the "SDCKB seizure-release" sequence. Each sequence is described below.
<Normal Sequence>
The following chart shows the flow of data between the CPU, the peripheral controller, and the peripheral device.
Fig. 5-1 Normal Sequence
<SDCKB Seizure-Release Sequence>
The SDCKB seizure-release sequence is used for latching the HV counter, primarily when using the Light Phaser Gun. The sequence is illustrated below.
Fig. 5-2 SDCKB Seizure-Release Procedure
Access Procedure
There are two access procedures, as described below: software initiated and hardware initiated.
* It is necessary for the initial settings for SH4-DMAC (setting DMA ch0 to DDT mode) to already have been made before initiating Maple-DMA. (Refer to the DMAC item in section 2.2.3.)
<<Software initiation>>
~ Initialization ~
Initiation trigger ® Software
~ Effective procedure ~
~ Confirmation of end ~
Hardware initiation (auto-initiation at each trigger)
～Initialization～
1. System memory area protection register setting
Address: 0x005F6C8C Write data:0xXXXXXXXX
2. System control register setting
Address: 0x005F6C80 Write data:0x3A9800XX
[Timeout: 300[micro]s; initiation at each V-Blank Out; transfer rate: 2Mbps; initiation delay setting: XX]
3. DMA trigger selection register setting
Address: 0x005F6C10 Write data:0x00000001
Initiation trigger ® Hardware trigger (V-Blank Out)
～Execution Procedure～
4. Setting of data in system memory (DMA command table)
Address: System memory area 0xnnnnnnnn Write data:0x80000000
Send four bytes of data to port A and terminate.
Address: 0xnnnnnnnn + 0x4: Write data system memory address (0xmmmmmmmm)
Received data store address (0xmmmmmmmmm)
Address: 0xnnnnnnnn + 0x8 Write data: 0xXXXXXXXX
Data to be sent to port A: 0xXXXXXXXX
5. DMA command table address register setting
Address: 0x005F6C04 Write data: 0xnnnnnnnn
Starting address in system memory where the transmission data is stored
6. DMA enable register setting
Address: 0x005F6C14 Write data: 0x00000001
DMA enabled
7. DMA start/status register setting
Address: 0x005F6C18 Write data: 0x00000001
DMA initiation, transmission/reception start
～Ending Confirmation～
8. DMA start/status confirmation
Address: 0x005F6C18 Read data: Transmission/reception ends at 0x00000000
Transmission/reception end confirmation
9. Loading received data into system memory
Address: 0xmmmmmmmm Read data: 0xXXXXXXXX
Loading of received data from port A
Example of Transmission and Reception Data
Examples of a transmission data command file stored in system memory and the corresponding reception data are shown below.
(16 bytes of data are sent to portA, and the received data is stored in address 0x0C800000.)
Table 5-3
Table 5-3
Notes Regarding Access
Notes that need to be observed in accesses concerning register settings and data transfers are described below.
<<Concerning Register Settings>>
Concerning data transfer
Control Pad
The standard controller device IDs and data format are shown below.
<Device ID>
The device ID starts from the first data as shown below.
0x00-0x00-0x00-0x01-0x00-0x06-0x0F-0xFE-0x00-0x00-0x00-0x00-0x00-0x00-0x00-0x00
Table 5-4
<Read Data Format>
The data format size is 8 bytes.
Table 5-5
In the table, "Ra" indicates "right," "La" indicates "left," "Da" indicates "Down," and "Ua" indicates "Up."
1st: Digital button data (On = 0, Off = 1)
2nd: Digital button data (On = 0, Off = 1)
3rd: Analog axis 1 data (value of 0x00 « 0xFF)
4th: Analog axis 2 data (value of 0x00 « 0xFF)
5th: Analog axis 3 data (value of 0x00 « 0x80 « 0xFF)
6th: Analog axis 4 data (value of 0x00 « 0x80 « 0xFF)
7th: Analog axis 5 data (value of 0x00 « 0x80 « 0xFF)
8th: Analog axis 6 data (value of 0x00 « 0x80 « 0xFF)
<Write data format>
Because the target is a controller, there is no write data format. Writing data to the controller generates no response.
The hardware includes one port consisting of two lines, SDCKA and SDCKB, and data transfers are performed in synchronous serial mode. Data is transferred through half-duplex bi-directional transfer with a maximum data transfer rate of 2Mbps and a minimum data transfer rate of 250Kbps. The minimum data transfer unit is one frame, each of which begins with the START pattern that is indicated at the beginning of the data transfer, followed by a DATA pattern ranging in length from 4 to 1024 bytes, the parity bit, and then the END pattern. The eight parity bits are added automatically by the hardware when the data is sent, and are removed when the data is received.
The following register sets are provided for the Maple interface. (Details on each register are provided in the list of registers.)
- Maple-DMA Control Registers
- Maple I/F Block Control Registers
- Maple-DMA Secret Register
- Maple-DMA Debug Registers
- Maple I/F Block Hardware Control Register
- Maple I/F Block Hardware Test Registers
- Interrupt Control Registers ...interrupt related registers (SB_ISTNRM, etc.)
A command file is set up in system memory, containing the instructions (settings such as the communications port selection, the received data storage address, and the transfer data length) for the Maple controller and the transmission data. The command file consists of units formed by "instruction to the controller," "received data storage address," and "transmission data," in that order. Each of these units are located consecutively in system memory.
The controller can be started up by two methods: by software, or by hardware in synchronization with the V-BLANK signal. These methods are selected through the trigger selection register (SB_MDTSEL). When startup by the V-BLANK signal is selected, delayed startup can be selected through the system register (SB_MSYS) setting.
When the DMA enable register (SB_MDEN) and the DMA start register (SB_MDST) have been set by the SH4, the controller starts up and loads in the command file. The controller follows the instructions, sending the transmission data in system memory indicated by the DMA command table address register (SB_MDSTAR) in the specified length to the target port, and then waits to receive a response. When data is received, the controller writes that data in system memory, starting from the received data store address that was set in the instructions. After receiving data, the controller continues executing the instructions in sequence until it detects the end of the command file. (Accesses between the controller and system memory are all performed through DMA in ch0-DDT mode, and data is sent and received in units of 32 bytes.)
If, as a result of being disconnected or some other problem, the peripheral device does not respond (times out), then 0xFFFFFFFF is written to the first 32 bits of the received data storage address as "disconnected" processing. 0xFFFFFF00 is written if a parity error occurs during reception of serial data.
- Instruction Format
| bit 31 | 30-18 | 17-16 | 15-11 | 10-8 | 7-0 |
| End Flag | 000 0000 0000 00 | Port Select | 0000 0 | Pattern | Transfer Length |
Instructions to the Maple interface consist of 32 bits of data as shown above, and are set up in system memory.
An instruction consists of an End Flag bit, which indicates the end of the command file; the Port Select bits, which select the active port that is the target of the transmission/reception operation; the Pattern selection bits; and the Transfer Length bits.
When Maple detects a "1" in the End Flag bit, it terminates processing with this instruction. (The End Flag must be set to "1" in the last instruction in the transmission data.) When the pattern selection bits are set to "000," Maple outputs the data that is to be sent. If any other pattern is selected, the port outputs the information pattern only, and the transmission data length specification becomes invalid. "111" (NOP) is used to extend processing for a certain length of time. when the pattern "010" (Light-Gun mode) is selected, the End Flag bit of that instruction must be set to "1". All subsequent instructions are invalid until the pattern "100" (return from Light-Gun mode) is detected.
End Flag: Command file end bit
Setting | Meaning |
| 0 | Not end of command file |
| 1 | End of command file (Execution ceases after this command.) |
Port Select: Port selection bits… These bits select the port that is the target of the transmission/reception operation.
Setting | Selected port |
| 0 | Port A |
| 1 | Port B |
| 2 | Port C |
| 3 | Port D |
Pattern: Pattern selection bits
Pattern | Pattern | ||
| bit2 | bit1 | bit0 | |
| 0 | 0 | 0 | Normal data of the length indicated by Transfer Length |
| 0 | 1 | 0 | Light-Gun mode (Seizes SDCKB.) |
| 0 | 1 | 1 | RESET |
| 1 | 0 | 0 | Return from Light-Gun mode (Releases SDCKB.) |
| 1 | 1 | 1 | NOP (Waits after data is received before sending the next data.) |
Transfer Length: Transfer data length selection bits
Setting | Transfer data length |
| 0 | 4 Byte |
| 1 | 8 Byte |
| ： | ： |
| 0xFE | 1020 Byte |
| 0xFF | 1024 Byte |
- Received data storage address
Data is received from peripheral devices in 4-byte units, and is first loaded in a 32-byte reception FIFO. As soon as the FIFO becomes full, the data is transferred to the received data storage address in system memory. However, as soon as reception ends, even if the FIFO buffer is not full, an remaining data is regarded as invalid data and is transferred as 32 bytes.
The received data storage address area is from 0x00C00000 to 0x00FFFFE0 in system memory. (Specify "0" for the lower five bits of the address that indicates the 32 bytes that are transferred.)
- Transmission data
Register Map
The registers that are used only by the Maple interface are in the area (from 0x005F 6C00 to 0x005F 6CFF) described in the system mapping table in section 2.1.
The mapping of the registers that are used by Maple is shown below. (Refer to section 8.4.1.2 for details on individual registers.)
| Address | Register Name | Access | Function | Reset Initialize |
| Maple-DMA Control Registers (0x005F6C04, 0x005F6C14~18) | ||||
| 0x005F 6C00 | — | — | ||
| 0x005F 6C04 | SB_MDSTAR | R/W | DMA Command Table Address | not initialize |
| 0x005F 6C08 | - | - | ||
| 0x005F 6C0C | - | - | ||
| 0x005F 6C10 | SB_MDTSEL | R/W | DMA Trigger Selection | 0 |
| 0x005F 6C14 | SB_MDEN | R/W | DMA Enable | 0 |
| 0x005F 6C18 | SB_MDST | R/W | DMA Start / Status | 0 |
| Maple I/F Block Hardware Test Registers (0x005F6C70~7C, 0x005F6CE0~E4) | ||||
| Maple I/F Block Control Registers (0x005F6C80~84) | ||||
| 0x005F 6C80 | SB_MSYS | R/W | Maple System Control | 0x3A980000 |
| 0x005F 6C84 | SB_MST | R/- | Maple Status | |
| 0x005F 6C88 | SB_MSHTCL | /W | Maple Status Hard Trigger Clear | 0 |
| Maple-DMA Secret Register (0x005F6C8C) | ||||
| 0x005F 6C8C | SB_MDAPRO | -/W | Maple Sys.Mem. Area Protection | 0x00007F00 |
| Maple I/F Block Hardware Control Register (0x005F6CE8) | ||||
| 0x005F 6CE8 | SB_MMSEL | R/W | Maple MSB Selection | 1 |
| Maple-DMA Debug Registers (0x005F6CF4~FC) | ||||
| 0x005F 6CF4 | SB_MTXDAD | R/- | Maple TXD Address Counter | not initialize |
| 0x005F 6CF8 | SB_MRXDAD | R/- | Maple RXD Address Counter | not initialize |
| 0x005F 6CFC | SB_MRXDBD | R/- | Maple RXD Base Address | not initialize |
Table 5-1 Maple Register Map
* In the above table, in the "Reset Initialize" column, "Not Initialized" indicates that the register value is undefined after a system reset. In all other cases, the value shown indicates the value that is set in that register after a system reset.
Operating Sequence
There are two interface operating sequences: the normal sequence, and the "SDCKB seizure-release" sequence. Each sequence is described below.
<Normal Sequence>
The following chart shows the flow of data between the CPU, the peripheral controller, and the peripheral device.
Fig. 5-1 Normal Sequence
<SDCKB Seizure-Release Sequence>
The SDCKB seizure-release sequence is used for latching the HV counter, primarily when using the Light Phaser Gun. The sequence is illustrated below.
Fig. 5-2 SDCKB Seizure-Release Procedure
Access Procedure
There are two access procedures, as described below: software initiated and hardware initiated.
* It is necessary for the initial settings for SH4-DMAC (setting DMA ch0 to DDT mode) to already have been made before initiating Maple-DMA. (Refer to the DMAC item in section 2.2.3.)
<<Software initiation>>
~ Initialization ~
- Work RAM area protection register setting
Address: 0x005F 6C8C Write data: 0xXXXX XXXX - System control register setting
- DMA trigger selection register settings
Address: 0x005F 6C10 Write data: 0x00000000
Initiation trigger ® Software
~ Effective procedure ~
- Data setting in system memory (DMA command table)
Address: System memory area (0xnnnn nnnn) Write data: 0x8000 0000
Send four bytes of data to port A and terminate
Address: 0xnnnn nnnn + 4h Write data: System memory address (0xmmmm mmmm)
Contents: Received data storage address (0xmmmm mmmm)
Address: 0xnnnn nnnn + 8h Write data: 0xXXXX XXXX
Contents: Data to be sent to port A 0xXXXX XXXX - DMA command table address register setting
Address: 0x005F 6C04 Write data: 0xnnnn nnnn
Contents: Starting address where transmission data is to be stored in system memory (0xnnnn nnnn) - DMA enable register setting
Address: 0x005F 6C14 Write data: 0x0000 0001
Contents: DMA enable - DMA start/status register setting
Address: 0x005F 6C18 Write data: 0x0000 0001
Contents: DMA initiation, transmission/reception start
~ Confirmation of end ~
- DMA start/status confirmation
Address: 0x005F 6C18 Read data: 0x0000 0000 (transmission/reception end)
Contents: Confirmation of transmission/reception end - Loading received data into system memory
Address: 0xmmmm mmmm Read data: 0xXXXX XXXX
Load data that was received from port A
Hardware initiation (auto-initiation at each trigger)
～Initialization～
1. System memory area protection register setting
Address: 0x005F6C8C Write data:0xXXXXXXXX
2. System control register setting
Address: 0x005F6C80 Write data:0x3A9800XX
[Timeout: 300[micro]s; initiation at each V-Blank Out; transfer rate: 2Mbps; initiation delay setting: XX]
3. DMA trigger selection register setting
Address: 0x005F6C10 Write data:0x00000001
Initiation trigger ® Hardware trigger (V-Blank Out)
～Execution Procedure～
4. Setting of data in system memory (DMA command table)
Address: System memory area 0xnnnnnnnn Write data:0x80000000
Send four bytes of data to port A and terminate.
Address: 0xnnnnnnnn + 0x4: Write data system memory address (0xmmmmmmmm)
Received data store address (0xmmmmmmmmm)
Address: 0xnnnnnnnn + 0x8 Write data: 0xXXXXXXXX
Data to be sent to port A: 0xXXXXXXXX
5. DMA command table address register setting
Address: 0x005F6C04 Write data: 0xnnnnnnnn
Starting address in system memory where the transmission data is stored
6. DMA enable register setting
Address: 0x005F6C14 Write data: 0x00000001
DMA enabled
7. DMA start/status register setting
Address: 0x005F6C18 Write data: 0x00000001
DMA initiation, transmission/reception start
～Ending Confirmation～
8. DMA start/status confirmation
Address: 0x005F6C18 Read data: Transmission/reception ends at 0x00000000
Transmission/reception end confirmation
9. Loading received data into system memory
Address: 0xmmmmmmmm Read data: 0xXXXXXXXX
Loading of received data from port A
Example of Transmission and Reception Data
Examples of a transmission data command file stored in system memory and the corresponding reception data are shown below.
(16 bytes of data are sent to portA, and the received data is stored in address 0x0C800000.)
| Transmission data command file in system memory | ||
| Address | Data | Contents |
| +0x0 | 0x03 | Maple-Host Logic Command 32bit ・PortA ・Data 16Byte |
| +0x1 | 0x00 | |
| +0x2 | 0x00 | |
| +0x3 | 0x80 | |
| +0x4 | 0x00 | Recieve Data Destination Address 32bit |
| +0x5 | 0x00 | |
| +0x6 | 0x80 | |
| +0x7 | 0x0C | |
| +0x8 | COMMAND | Protocol Data 8bit |
| +0x9 | Destination AP | 〃 |
| +0xA | Source AP | 〃 |
| +0xB | Data Size | 〃 |
| +0xC | DATA0 | 〃 |
| +0xD | DATA1 | 〃 |
| +0xE | DATA2 | 〃 |
| +0xF | DATA3 | 〃 |
| +0x10 | DATA4 | 〃 |
| +0x11 | DATA5 | 〃 |
| +0x12 | DATA6 | 〃 |
| +0x13 | DATA7 | 〃 |
| +0x14 | Lower Byte0 | 〃 16bit |
| +0x15 | Upper Byte0 | |
| +0x16 | Lower Byte1 | 〃 16bit |
| +0x17 | Upper Byte1 |
Table 5-3
| Received data stored in system memory | |||
| Address | Data | Contents | |
| 0x0C800000 | COMMAND | Protocol Data 8bit | |
| 0x0C800001 | Destination AP | 〃 | |
| 0x0C800002 | Source AP | 〃 | |
| 0x0C800003 | Data Size | 〃 | |
| 0x0C800004 | DATA0 | 〃 | |
| 0x0C800005 | DATA1 | 〃 | |
| 0x0C800006 | DATA2 | 〃 | |
| 0x0C800007 | DATA3 | 〃 | |
| 0x0C800008 | DATA4 | 〃 | |
| 0x0C800009 | DATA5 | 〃 | |
| 0x0C80000A | DATA6 | 〃 | |
| 0x0C80000B | DATA7 | 〃 | |
| 0x0C80000C | Lower Byte0 | 〃 16bit | |
| 0x0C80000D | Upper Byte0 | ||
| 0x0C80000E | Lower Byte1 | 〃 16bit | |
| 0x0C80000F | Upper Byte1 |
Table 5-3
Notes Regarding Access
Notes that need to be observed in accesses concerning register settings and data transfers are described below.
<<Concerning Register Settings>>
- If the controller is waiting for a single hardware trigger to clear, and then the initiation trigger is set to the software trigger and then back to a hardware trigger again, the hardware trigger that was set last is valid. (If DMA was not disabled at the moment that the switch was made to the hardware trigger, the trigger is not overwritten, and the wait for the single hardware trigger to clear becomes invalid.)
- Regarding forced termination through the DMA enable register（SB_MDEN）, when sending or receiving data, termination does not occur until transmission/reception on that port is completed. Therefore, it is possible for several DMA transfers to still occur after DMA is disabled. In addition, because a DMA end interrupt is not generated, the end must be detected only by polling the status. However, in the case of a forced termination as a result of an illegal error (for example, if system memory area protection was violated), the DMA ends at that point (when the error interrupt is generated).
- The DMA trigger selection register (SB_MDTSEL) and the system control register (SB_MSYS) cannot be overwritten while DMA is enabled.
- An illegal address error interrupt is generated when a value other than that specified by the system memory area protection register (SB_MDAPRO) is written to the DMA command table address register (SB_MDSTAR), and when an attempt is made to initiate DMA while in that state. An illegal address error interrupt is not generated when setting the received data store address that is written to system memory as a command, or when fetching a peripheral controller. An overrun error interrupt is generated when system memory is accessed. (It is not generated in the DMA write cycle.) The system control register cannot be overwritten while DMA is enabled.
- The DMA start/status register (SB_MDST) indicates that V-Blank Out initiated the operation during delayed initiation by the hardware trigger. Bit 31 of the status register (SB_MST) indicates that operation is in progress based on the actual timing of transmission/reception after the delay. (This bit indicates that no operation is in progress from the time of V-Blank Out to the end of the delay.)
- The system control register initiation delay setting is valid only for the hardware trigger, and is invalid for the software trigger.
Concerning data transfer
- When more than one frame of data (1024 bytes) has been sent, forced termination results and processing continues as if a parity error had occurred.
- Repeated transmission/reception is possible by placing transmission commands consecutively in system memory. In addition, consecutive transmission/reception through the same port is possible by inserting several NOP instructions. (One instruction generates an interval of about 160[micro]s between accesses.)
- Received data must be written in units of 32 bytes. If, for example, 36 bytes of data are received, valid data will be written in the first 36 bytes following the "received data storage address," and invalid data will be written in the remaining 28 bytes. Transmission commands can be stored consecutively in units of 4 bytes.
- Regarding the reception buffer in system memory, the received data is asynchronous, and a maximum of 1024 bytes of data can be received. The length of the received data is normally controlled by the protocol, but it is possible that the actual length will exceed the intended length due to errors, etc. Therefore, important data should not be stored in the 1024 bytes after the final "received data storage address."
- Data transfers between the peripheral controller and peripheral devices are performed in units of 32 bits, but the transmission data in this case is sent starting from the MSB (bit 31). Therefore, in a system that uses the Little Endian configuration, the data is sent starting from the MSB (bit 7) of the uppermost byte in four bytes of data, working down towards the lower bytes. In the same manner, received data is stored in units of 4 bytes, from the upper bytes to the lower bytes, starting with the data that was received first.
- When a data transmission/reception spans a V-Blank, a V-Blank Over interrupt is generated, but the transmission/reception continues and the data is guaranteed.
Control Pad
The standard controller device IDs and data format are shown below.
<Device ID>
The device ID starts from the first data as shown below.
0x00-0x00-0x00-0x01-0x00-0x06-0x0F-0xFE-0x00-0x00-0x00-0x00-0x00-0x00-0x00-0x00
| bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 | |
| 1st Data | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 2nd Data | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 3rd Data | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 4th Data | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
| 5th Data | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 6th Data | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 |
| 7th Data | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 |
| 8th Data | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 |
| 9th Data | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 10th Data | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 11th Data | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 12th Data | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 13th Data | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 14th Data | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 15th Data | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 16th Data | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Table 5-4
<Read Data Format>
The data format size is 8 bytes.
| bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 | |
| 1st Data | Ra | La | Da | Ua | Start | A | B | 1 |
| 2nd Data | 1 | 1 | 1 | 1 | 1 | X | Y | 1 |
| 3rd Data | A17 | A16 | A15 | A14 | A13 | A12 | A11 | A10 |
| 4th Data | A27 | A26 | A25 | A24 | A23 | A22 | A21 | A20 |
| 5th Data | A37 | A36 | A35 | A34 | A33 | A32 | A31 | A30 |
| 6th Data | A47 | A46 | A45 | A44 | A43 | A42 | A41 | A40 |
| 7th Data | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 8th Data | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Table 5-5
In the table, "Ra" indicates "right," "La" indicates "left," "Da" indicates "Down," and "Ua" indicates "Up."
1st: Digital button data (On = 0, Off = 1)
2nd: Digital button data (On = 0, Off = 1)
3rd: Analog axis 1 data (value of 0x00 « 0xFF)
4th: Analog axis 2 data (value of 0x00 « 0xFF)
5th: Analog axis 3 data (value of 0x00 « 0x80 « 0xFF)
6th: Analog axis 4 data (value of 0x00 « 0x80 « 0xFF)
7th: Analog axis 5 data (value of 0x00 « 0x80 « 0xFF)
8th: Analog axis 6 data (value of 0x00 « 0x80 « 0xFF)
<Write data format>
Because the target is a controller, there is no write data format. Writing data to the controller generates no response.
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- SWAT
- 01 декабря 2010, 09:25
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